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ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 8-12 Years | Pune)
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View JobASIC Engineering Layout Leader | Custom IC layout, Analog, Mixed-signal, and high-speed designs | 12+ years, Bangalore
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View JobTechnical Leader - C/C++, Device Driver, Kernel, Multithreading, Embedded Systems - 10 to 13 years - Bangalore
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View JobASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |12-16 years| Pune)
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