Location
Santa Clara
Job Type
Full-time
Posted
July 08, 2026
Job Description
**Job Details:**
**Job Description:**
+ Defines, architects, and documents verification strategy and methodologies for implementing and verifying the silicon design in the most optimal manner.
+ Architects the testbenches and develops universal verification methodology (UVM) or formal based verification approaches. Integrates the block testbench in chiplevel UVM environment and verifies integration.
+ Develops test strategy, test bench architecture, and test plans for design blocks to conform to specifications.
+ Enables interaction with analog and digital teams and supports postsilicon validation activities.
+ Collaborates with the architecture and design team to create random test generation plans, runs functional simulation to identify gaps in design specification, and conducts failure analysis, coverage analysis, and closure.
+ Defines and develops the security validation strategy and validation infrastructure to incorporate security tools and metho...
**Job Description:**
+ Defines, architects, and documents verification strategy and methodologies for implementing and verifying the silicon design in the most optimal manner.
+ Architects the testbenches and develops universal verification methodology (UVM) or formal based verification approaches. Integrates the block testbench in chiplevel UVM environment and verifies integration.
+ Develops test strategy, test bench architecture, and test plans for design blocks to conform to specifications.
+ Enables interaction with analog and digital teams and supports postsilicon validation activities.
+ Collaborates with the architecture and design team to create random test generation plans, runs functional simulation to identify gaps in design specification, and conducts failure analysis, coverage analysis, and closure.
+ Defines and develops the security validation strategy and validation infrastructure to incorporate security tools and metho...