Formal Verification Engineer

<p><b>Job Description:</b></p> <p>We are looking for formal verification experts to ensure design correctness using mathematical verification techniques and advanced formal tools.</p> <p><b>Key Responsibilities:</b></p> <ul> <li>Develop formal verification strategies and methodologiesWrite SystemVerilog Assertions (SVA)</li> <li>Perform property checking, equivalence checking, and CDC/RDC analysis</li> <li>Identify corner cases missed in simulation</li> <li>Collaborate with RTL teams for design improvements</li> </ul> <p><b>Required Skills:</b></p> <ul> <li>Strong knowledge of formal verification tools (Jasper, VC Formal, etc.)</li> <li>Expertise in SVA and property specification</li> <li>Solid understanding of digital design and logic reasoning</li> </ul> <p><b>Good to Have:</b>...