Hybrid ASIC Verification Engineer (SystemVerilog/UVM)

A leading technology company is seeking an ASIC Digital Verification Engineer in Espoo, Finland. In this role, you will support the verification of Mixed‑Signal or System‑on‑Chip ASICs and contribute to the development of reusable verification environments. Candidates should have experience with SystemVerilog and UVM, along with a degree in electrical engineering or computer science. The position offers the opportunity to work in a hybrid format as well as within a global team.
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