Hybrid FPGA/ASIC RTL Design Engineer

Intel is looking for an Experienced Hire to develop and maintain RTL designs using Verilog/System Verilog for FPGA and ASIC solutions in Malaysia, Penang. The role demands strong experience in RTL design with a focus on debugging and collaboration.

Ideal candidates will have 5+ years in RTL design, proficiency in Verilog, and familiarity with various logic design tools. The position offers a hybrid work model to allow flexibility in your working environment.