Hybrid FPGA/ASIC RTL Design Engineer - Verilog

A leading technology company in Malaysia is seeking an experienced RTL designer to develop and maintain designs using Verilog/System Verilog for FPGA and ASIC solutions. The ideal candidate will have over 5 years of RTL/Logic design experience and knowledge in packet-based protocols. Strong analytical and problem-solving skills are essential. This role offers a hybrid work model, allowing employees to split their time between on-site and remote work.
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