Lead Memory Design Engineer

ACL Digital ยท Bengaluru, Karnataka, India

Location
Bengaluru
Job Type
Full-time
Posted
June 04, 2026

Job Description

๐—Ÿ๐—ฒ๐—ฎ๐—ฑ ๐— ๐—ฒ๐—บ๐—ผ๐—ฟ๐˜† ๐——๐—ฒ๐˜€๐—ถ๐—ด๐—ป ๐—˜๐—ป๐—ด๐—ถ๐—ป๐—ฒ๐—ฒ๐—ฟ


๐—ฅ๐—ฒ๐˜€๐—ฝ๐—ผ๐—ป๐˜€๐—ถ๐—ฏ๐—ถ๐—น๐—ถ๐˜๐—ถ๐—ฒ๐˜€:

As Memory Design Engineer, we will work on developing memory compilers and memory Fast Cache instances for our next generation Cores achieving outstanding PPA.


๐—ฅ๐—ฒ๐—พ๐˜‚๐—ถ๐—ฟ๐—ฒ๐—ฑ ๐—ฆ๐—ธ๐—ถ๐—น๐—น๐˜€ ๐—ฎ๐—ป๐—ฑ ๐—˜๐˜…๐—ฝ๐—ฒ๐—ฟ๐—ถ๐—ฒ๐—ป๐—ฐ๐—ฒ :

๐Ÿ”ธ Understanding of computer architecture and concepts.

๐Ÿ”ธ Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis and Monte Carlo Simulations.

๐Ÿ”ธ Good experience in design verification: Sense amplifier analysis, self-time analysis and marginality analysis.

๐Ÿ”ธ Understanding of high speed/low power CMOS circuit design, clocking scheme, Static and complex logic circuits.

๐Ÿ”ธ Understanding of Power versus Performance versus Area trade-offs in typical CMOS design.

๐Ÿ”ธ Strong knowledge of physical implementation impact on circuit performance.

๐Ÿ”ธ Good understanding of high-performance and low power circuit designs with exposure to FinFet technolog...

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