Lead PCS RTL Design Engineer — Hybrid & Flexible Hours

Hireroo is looking for a Lead PCS Design Engineer in Barcelona, Spain. This role involves designing RTL for PCS and FEC blocks and working on Ethernet integration within a hybrid working model. Responsibilities include mentoring engineers and translating architecture requirements into Verilog or VHDL. Candidates should have a Bachelor’s degree in a related field and strong experience in PCS, FEC, and Verilog, as well as proficient problem-solving skills. The company offers flexible working hours and various benefits including private medical insurance and a relocation bonus.
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