Job Description
About the Company
Our client is a fast growing chip design company based in Singapore. The Company has strong R&D capabilities and the core technical team members all have numerous years of experience in the semiconductor industry. We have rich industry experience and deep practical accumulation in IC design and business management. (Fresh EEE graduate from local Singapore universities welcome to apply)
About the Role
Works with the front-end design team to complete the chip floorplan, clock architecture, and powerplan. Takes charge of the physical design tasks from the Netlist to the GDSII, including P&R, formal verification, static timing analysis, physical verification, power analysis, design for reliability and tapeout.
Responsibilities
- Complete the chip floorplan
- Design clock architecture
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