Location
Cary
Job Type
Full-time
Posted
July 05, 2026
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are a small group of individuals designing among the most complex chip in the world getting into the award-winning Cadence Design Systems Palladium platform…
As such we are seeking an experienced DFT engineer which role will span across the full spectrum of the DFT implementation: from architecture definition through silicon testing and debug.
A bonus, this individual will have cross functional teams’ interactions not only within our group; but across Cadence and the multiple BU involved in our developments.
Key responsibilities:
+ Define and implement SoC level DFT architecture for large and complex designs.
+ Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG.
+ Perform DFT insertion, verification, and coverage analysis at block and SoC levels.
+ Drive pre-silicon DFT sign-off, includi...
We are a small group of individuals designing among the most complex chip in the world getting into the award-winning Cadence Design Systems Palladium platform…
As such we are seeking an experienced DFT engineer which role will span across the full spectrum of the DFT implementation: from architecture definition through silicon testing and debug.
A bonus, this individual will have cross functional teams’ interactions not only within our group; but across Cadence and the multiple BU involved in our developments.
Key responsibilities:
+ Define and implement SoC level DFT architecture for large and complex designs.
+ Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG.
+ Perform DFT insertion, verification, and coverage analysis at block and SoC levels.
+ Drive pre-silicon DFT sign-off, includi...
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