RTL Design Engineer for Memory/PHY at AMD

Join AMD in Vancouver as an RTL Design Engineer, where you will lead RTL design for memory/PHY subsystems. Enhance next-gen computing through innovative digital solutions.
This role is ideal for an experienced engineer with a knack for driving design work across teams. You'll develop complex silicon IP, ensuring top-notch performance while adhering to JEDEC DDR specifications. This is a hands-on role for those passionate about technical leadership and collaboration.
Key Responsibilities:
• Drive microarchitectural design for memory subsystems
• Collaborate with teams on firmware and design optimization
• Ensure compliance with DDR specifications
• Analyze RTL for optimization strategies
• Introduce new EDA tools and methods
Requirements:
• Solid digital design engineering background
• Expertise in DDR/LPDDR memory controller design
• Strong Verilog/SystemVerilog skills
• Familiarity with simulation tools and methodologies
• Bachelor’s or Master’s ...