Semiconductor Process Engineering – Wet Etch & CMP

Role Overview

We are seeking a Wet Etch & Chemical Mechanical Planarisation (CMP) Process Engineer to support and develop advanced semiconductor manufacturing processes within a high‑volume wafer fabrication environment.

All experience levels will be considered however strong preference is given to candidates with significant experience and seniority, capable of operating with minimal supervision and providing technical leadership. Experience with wet/CMP techniques is a prerequisite for this role.

The role will suit candidates from a wafer fab or semiconductor equipment vendor background, particularly those with experience in power semiconductor technologies. Experience with SiC and GaN technologies is desirable but not essential.

Key Responsibilities