Senior design verification engineer

Hiring: PCIe Verification Engineer | Bangalore | 5+ Years
We are hiring PCIe Verification Engineers for Bangalore location with strong hands-on experience in System Verilog & UVM and deep understanding of PCIe protocol.
Location
Bangalore
⏳ Experience
5+ Years
Key Responsibilities
Develop UVM-based testbench & verification environments
Create test plans, testcases, sequences & coverage models
Perform protocol-level verification (PCIe layers – PHY, DLL, TL)
Debug issues using waveforms, logs & assertions
Work on regression, coverage closure & sign-off activities
Required Skills
Strong expertise in System Verilog & UVM
Hands-on experience in PCIe (Gen3/4/5/6)
Experience in testbench development & debugging
Good understanding of digital design concepts
Exposure to simulation tools (VCS / Questa / Xcelium)
Good to Have
Experience with So C/Sub-system level verification
Scripting knowledge ( Python / Perl / TCL )
Knowledge of C/...