Senior IC Verification Engineer — UVM/SV Expert

ETHOS TECH ONE PTE. LTD. is seeking an engineer in Singapore to develop and review test plans based on IC design specifications. The ideal candidate should have a Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering and at least 1 year of experience in Silicon verification using SystemVerilog and UVM.

The role involves creating verification environments, debugging tests, and ensuring product performance. Strong analytical skills and understanding of HDL are essential. Familiarity with EDA tools such as Cadence and Synopsys is also required.