Senior PCIe IP RTL Engineer — Design & Verification

Bitdeer in Singapore is looking for a PCIe IP Design Engineer to develop Verilog RTL for PCIe-related IP blocks. The role includes ensuring functional coverage, contributing to both pre-silicon and post-silicon debug activities, and collaborating with verification teams.

The ideal candidate should have a Master’s or Bachelor’s degree in Electrical or Computer Engineering, five years of semiconductor experience, and Verilog RTL development skills. This role offers opportunities for personal accountability and professional growth in a fast-paced environment.