Senior PMIC RTL Verification Engineer

A leading technology company in Malaysia, Penang is seeking a Senior Logic Design Verification Engineer. You will define and develop verification testbench, validate new designs, and collaborate across teams. The ideal candidate has extensive experience in design verification, specifically with UVM and System Verilog, and demonstrates strong analytical and problem-solving skills. This role requires an on-site presence.
#J-18808-Ljbffr