SoC Verification Lead: Strategy, UVM & Debug Excellence

Altera is seeking a Design Verification Lead to oversee SoC architecture verification in Penang, Malaysia. This role involves creating verification strategies, developing test cases, and leading cross-functional efforts to ensure thorough verification plans.

The ideal candidate will have over 12 years of experience, proficiency in SystemVerilog and UVM methodology, and strong communication skills to collaborate with globally dispersed teams.