Staff IP Design Engineer: High-Speed FPGA & SerDes

A leading technology company in Malaysia is seeking a Staff IP Design Engineer to build Connectivity IP portfolios for FPGAs. The ideal candidate will have strong technical leadership, experience with high-speed SERDES protocols, and programming skills in languages such as C/C++ and Python. Candidates should also have a minimum of 8 years of relevant experience and be able to work well within a diverse team, driving projects to completion. A commitment to innovation and problem-solving is essential in this fast-paced environment.
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